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Proceedings of SLIP'03 : 2003 international workshop on system level interconnect prediction, Dobletree Hotel, Monterey, California, USA, April 5-6, 2003 /
Published 2003
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Mosfet modeling for VLSI simulation : theory and practice /
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Arora, Narain
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Harnessing VLSI system design with EDA tools /
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Symbolic analysis and reduction of VLSI circuits /
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Principles of verifiable RTL design : a functional coding style supporting verification processes in Verilog /
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Call Number: T - Technology
Library: mai
Suggested Topics: Integrated circuits
Suggested Topics: Very large scale integration
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KMUTT
(6)
Library
mai
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MONOGRAPHS
(5)
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Call Number
T - Technology
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Arora, Narain
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Bening, Lionel
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Iniewski, Krzysztof
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Qin, Zhanhai
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